Draft:Peter Flake

  • Comment: Well done on creating the draft, and it may potentially meet the relevant requirements (including WP:GNG, WP:ANYBIO, WP:NPROF) but presently it is not clear that it does.
    As you may know, Wikipedia's basic requirement for entry is that the subject is notable. Essentially subjects are presumed notable if they have received significant coverage in multiple published secondary sources that are reliable, intellectually independent of each other, and independent of the subject. To properly create such a draft page, please see the articles ‘Your First Article’, ‘Referencing for Beginners’ and ‘Easier Referencing for Beginners’.
    The draft does not appear to show that the subject has any notability beyond the average coverage in trade publications for similar researchers (see WP:ROTM).
    Also, if you have any connection to the subject, including being the subject (see WP:AUTOBIO) or being paid, you have a conflict of interest that you must declare on your Talk page (to see instructions on how to do this please click the link).
    Please familiarise yourself with these pages before amending the draft. If you feel you can meet these requirements, then please make the necessary amendments before resubmitting the page. It would help our volunteer reviewers by identifying, on the draft's talk page, the WP:THREE best sources that establish notability of the subject.
    It would also be helpful if you could please identify with specificity, exactly which criteria you believe the page meets (eg "I think the page now meets WP:ANYBIO criteria #3, because XXXXX").
    Once you have implemented these suggestions, you may also wish to leave a note for me on my talk page and I would be happy to reassess. Cabrils (talk) 07:27, 21 June 2025 (UTC)

Peter L. Flake is a British computer scientist and electronic‑design‑automation (EDA) engineer best known for creating HILO, one of the first commercial hardware‑description‑language (HDL) simulators, and for co‑architecting Superlog, the language that evolved into SystemVerilog. During a career that has stretched from the 1970s to the 2020s he has moved between academia, start‑ups and large EDA vendors, shaping how engineers specify and verify digital systems.


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